Osprey E300
Aug 10, 2023
Basic Architecture The E300 is a device with three seperate boards, each one with a Xilinx XCVU35P FPGA, which all are connected to a single control board with a Xilinx Zynq XC7Z010 via a ribbon cable with a 20-pin header. Zynq devices are FPGA devices with hard (ASIC) ARM CPU cores integrated onto the same chip - the dual-core ARM CPU responsible for running Linux and such, while the FPGA side offers access to the hardware on the FPGA boards through the Linux environment.
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Polaris MVDD
Aug 10, 2023
AMD Polaris (RX 470/480/570/580) Memory Voltage AMD Polaris cards (including the RX 470, 480, 570, and 580 are said to have a fixed memory voltage (MVDD), and it is impossible for software to change this. This, however, is not true. First, I will cite a post which describes the power delivery of these cards fairly well, and asks about software modification of the voltage. Second, I will detail how it is possible to adjust the voltage from software.
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SQRL Forest Kitten 33 Details
Aug 10, 2023
Overview The SQRL Forest Kitten 33 has a xcvu33p-fsvh2104-2L-e FPGA (which may be ES0/ES1 (engineering sample). I only have the air-cooled version, so I can only comment on it, but the fan blades are somewhat fragile. Regardless of this, the heatsink/fan combination is adequate, even under higher load situations. One thing of note is that it is extremely easy to disassemble - very few screws, which are easy to access.
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Xilinx HBM2 Internals
Aug 10, 2023
Conventions MiB = Megabytes (2^20 bytes) Gb = Gigabits (2^27 bytes, or 128MiB) GiB = Gibibytes (2^30 bytes) Background on HBM2 HBM2 is a type of stacked memory, with each stack containing multiple DRAM dies (chips), and each die supporting 2 channels. Every channel accesses a different (and independent) set of DRAM banks - as a result, requests for one channel cannot access data from another channel. This can be thought of as each channel “owning” a certain address range.
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